SECTOR 01
Semiconductors & microelectronics
Where a 40 nm film decides a $40 m quarter.
Front-end and back-end problems where the material, not the design, is the variable that moved.
Semiconductor problems are unforgiving because the signal is buried in a process with hundreds of steps and enormous lot-to-lot noise. We are usually brought in when a yield excursion has survived the standard 8D process and the correlation analysis has produced three plausible suspects and no decision.
What we work on
- Thin-film adhesion, stress and delamination in interconnect stacks
- Organic and metallic contamination: source identification and transport path
- Wafer-level and package-level warpage from CTE mismatch
- Underfill, moulding compound and die-attach material qualification
- Wire bond and solder joint intermetallic growth
- Moisture sensitivity level failures and popcorning
Standards we work to
JEDEC JESD22 and J-STD-020, AEC-Q100 and Q006 for automotive parts, IPC-9701 for solder attach reliability, SEMI standards for materials and contamination control.